The present invention relates generally to the field of integrated circuits (ICs) and, in particular, to process, voltage and temperature (PVT) variations in ICs.
PVT variations are a critical factor that can hamper the performance of the ICs. For example, PVT variations can result in a change in setup and hold times of synchronous circuits. Different components of a synchronous circuit are driven by a common system clock. Therefore, a change in the setup or hold times corresponding to any one component can result in an erroneous circuit output. PVT variations can also result in a change in slew rates, increase in current leakage, and electromagnetic interference (EMI).
One technique for reducing PVT variations in a circuit is based on sensing variations in the operation of the circuit and taking appropriate action to reduce these variations. For example, if a variation in the signal delay is identified, then the input signal delay is changed accordingly to compensate for the variation. In other cases, delay variations in the circuit are monitored and bias voltages of P-metal oxide semiconductor (PMOS) and N-metal oxide semiconductor (NMOS) transistors of the circuit are changed depending on the delay variations.
Another technique to compensate for PVT variations of the circuit is based on open loop control. The circuit output is determined by a control value and the circuit output is compensated by regulating the control value so that it corresponds to typical input-output characteristics of the circuit.
Some of the techniques mentioned above provide the same compensation for PVT variations of both the PMOS and the NMOS transistors. However, PVT variations associated with the PMOS and the NMOS transistors may be quite different. Therefore, such techniques might not provide adequate compensation. Further, a memory is required to compensate for PVT variations. Finally, these techniques involve additional process steps, which are complex in nature.